System - Level Synthesis of Low - Power Hard Real - Time

The imminent convergence of computer, communications, and consumer electronic products and market implies a need for optimization intensive techniques for synthesis of low power hard real-time systems. In this paper, we present a system-level approach for power minimization under a set of user-speciied costs and timing constraints of hard real-time designs. The approach simultaneously optimizes all three degrees of freedom for power minimization, namely switching activity, eeective capacity and voltage supply. We rst deene two key associated optimization problems, processor allocation and task assignment, and establish their computational complexity. Next, we describe a novel meta-algorithmics algorithm development strategy. The strategy is used for evaluation and statistical validation of the key parameters that guide the heuristic assignment process. The statistical analysis of comprehensive experimental results and their comparison with the developed conservative and optimistic sharp lower bounds, clearly indicates the quality of the proposed optimization techniques.